FIG. 1 is an illustration of a conventional CMOS design 100. The conventional design 100 includes a substrate 102 and raised metal layers M1 through Mn. The Redistributed Design Layer (RDL) 101, in this example, includes metal oxide and, thus, can also be referred to as a metal layer. The raised metal layers M1 through Mn are fabricated during back end of the line processes and are referred to as Back End of the Line (BEOL) layers 103.
An active layer 106 is fabricated upon the substrate 102 and includes active devices such as the NMOS transistor 107 and the PMOS transistor 108. The substrate processing and active device fabrication occur during front end of line processes and are referred to as Front End of the Line (FEOL) layers.
The design 100 also includes an inductor 110, which is fabricated in one of the raised metal layers M1 through Mn. Thus, the inductor 110 sits in the BEOL metal layer stack directly above the active layer 106. FIG. 2 shows a simplified version of the design 100 showing a placement of the inductor 110 within the BEOL metal layer stack. Within the active layer 106, the area 105 is the area directly below the inductor 110. It should be noted that as used herein, “above” and “below” do not indicate an up/down directional relationship, but rather refer to placement in the stack. For example, BEOL components are referred to as above the substrate 102 or above the active layer 106, whereas the RDL 101 is referred to as below the substrate 102.
In the conventional design 100, the area 105 experiences high levels of electromagnetic interference from the inductor 110 such that the area 105 is unsuitable for active devices. The area 105 represents a large portion of space on the substrate 102 upon which active devices could otherwise be fabricated. In fact, in some conventional designs, an area equal to A×B (see FIG. 1) in the active layer 106 is unusable, and in current designs, A×B may be in the range of 300 microns by 300 microns—an area large enough to accommodate about 1,000,000 transistors. Conventional designs often have increased die sizes in order to accommodate amounts of wasted space lost due to placement of inductors. Wasted die space translates to increased costs. Currently, there is no effective and available technique to limit the amount of wasted space caused by passive devices such as inductors other than to limit the use of passive devices.